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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>FCMLA (by element) -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">FCMLA (by element)</h2>
      <p class="aml">Floating-point Complex Multiply Accumulate (by element).</p>
      <p class="aml">This instruction operates on complex numbers that are represented in SIMD&amp;FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on complex numbers from the first source register and the destination register with the specified complex number from the second source register:</p>
      <ul>
        <li>Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees.</li>
        <li>The two elements of the transformed complex number are multiplied by:<ul><li>The real element of the complex number from the first source register, if the transformation was a rotation by 0 or 180 degrees.</li><li>The imaginary element of the complex number from the first source register, if the transformation was a rotation by 90 or 270 degrees.</li></ul></li>
        <li>The complex number resulting from that multiplication is added to the complex number from the destination register.</li>
      </ul>
      <p class="aml">The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding.</p>
      <p class="aml">This instruction can generate a floating-point exception. Depending on the settings in <a class="armarm-xref" title="Reference to Armv8 ARM section">FPCR</a>, the exception results in either a flag being set in <a class="armarm-xref" title="Reference to Armv8 ARM section">FPSR</a> or a synchronous exception being generated. For more information, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Floating-point exception traps</a>.</p>
      <p class="aml">Depending on the settings in the <a class="armarm-xref" title="Reference to Armv8 ARM section">CPACR_EL1</a>, <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL2</a>, and <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL3</a> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</p>
    
    <h3 class="classheading"><a id="iclass_2reg_element"/>Vector<span style="font-size:smaller;"><br/>(FEAT_FCMA)
          </span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">Q</td><td class="lr">1</td><td class="l">0</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td colspan="2" class="lr">size</td><td class="lr">L</td><td class="lr">M</td><td colspan="4" class="lr">Rm</td><td class="lr">0</td><td colspan="2" class="lr">rot</td><td class="lr">1</td><td class="lr">H</td><td class="lr">0</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"><span class="bitdiff"> (size == 01)</span></h4><a id="FCMLA_asimdelem_C_H"/><p class="asm-code">FCMLA  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;size:Q&quot;) [4H,4S,8H]">&lt;T&gt;</a>, <a href="#sa_vn" title="First SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;size:Q&quot;) [4H,4S,8H]">&lt;T&gt;</a>, <a href="#sa_vm" title="Second SIMD&amp;FP source register (field &quot;M:Rm&quot;)">&lt;Vm&gt;</a>.<a href="#sa_ts" title="Element size specifier (field &quot;size&quot;) [H,S]">&lt;Ts&gt;</a>[<a href="#sa_index" title="Element index (field &quot;size:H:L&quot;) [H,H:L]">&lt;index&gt;</a>], #<a href="#sa_rotate" title="Rotation (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></p></div><div class="encoding"><h4 class="encoding"><span class="bitdiff"> (size == 10)</span></h4><a id="FCMLA_asimdelem_C_S"/><p class="asm-code">FCMLA  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;size:Q&quot;) [4H,4S,8H]">&lt;T&gt;</a>, <a href="#sa_vn" title="First SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;size:Q&quot;) [4H,4S,8H]">&lt;T&gt;</a>, <a href="#sa_vm" title="Second SIMD&amp;FP source register (field &quot;M:Rm&quot;)">&lt;Vm&gt;</a>.<a href="#sa_ts" title="Element size specifier (field &quot;size&quot;) [H,S]">&lt;Ts&gt;</a>[<a href="#sa_index" title="Element index (field &quot;size:H:L&quot;) [H,H:L]">&lt;index&gt;</a>], #<a href="#sa_rotate" title="Rotation (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-shared.HaveFCADDExt.0" title="function: boolean HaveFCADDExt()">HaveFCADDExt</a>() then UNDEFINED;
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(M:Rm);
integer index;
if size == '00' || size == '11' then UNDEFINED;
if size == '01' then index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(H:L);
if size == '10' then index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(H);
integer esize = 8 &lt;&lt; <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
if !<a href="shared_pseudocode.html#impl-shared.HaveFP16Ext.0" title="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() &amp;&amp; esize == 16 then UNDEFINED;
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;
if size == '10' &amp;&amp; (L == '1' || Q == '0') then UNDEFINED;
if size == '01' &amp;&amp; H == '1' &amp;&amp; Q == '0' then UNDEFINED;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vd&gt;</td><td><a id="sa_vd"/>
        
          <p class="aml">Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;T&gt;</td><td><a id="sa_t"/>
        <p>Is an arrangement specifier, 
      encoded in
      <q>size:Q</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">size</th>
                <th class="bitfield">Q</th>
                <th class="symbol">&lt;T&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">00</td>
                <td class="bitfield">x</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">01</td>
                <td class="bitfield">0</td>
                <td class="symbol">4H</td>
              </tr>
              <tr>
                <td class="bitfield">01</td>
                <td class="bitfield">1</td>
                <td class="symbol">8H</td>
              </tr>
              <tr>
                <td class="bitfield">10</td>
                <td class="bitfield">0</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">10</td>
                <td class="bitfield">1</td>
                <td class="symbol">4S</td>
              </tr>
              <tr>
                <td class="bitfield">11</td>
                <td class="bitfield">x</td>
                <td class="symbol">RESERVED</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vn&gt;</td><td><a id="sa_vn"/>
        
          <p class="aml">Is the name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vm&gt;</td><td><a id="sa_vm"/>
        
          <p class="aml">Is the name of the second SIMD&amp;FP source register, encoded in the "M:Rm" fields.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Ts&gt;</td><td><a id="sa_ts"/>
        <p>Is an element size specifier, 
      encoded in
      <q>size</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">size</th>
                <th class="symbol">&lt;Ts&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">00</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">01</td>
                <td class="symbol">H</td>
              </tr>
              <tr>
                <td class="bitfield">10</td>
                <td class="symbol">S</td>
              </tr>
              <tr>
                <td class="bitfield">11</td>
                <td class="symbol">RESERVED</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;index&gt;</td><td><a id="sa_index"/>
        <p>Is the element index, 
      encoded in
      <q>size:H:L</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">size</th>
                <th class="symbol">&lt;index&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">00</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">01</td>
                <td class="symbol">H:L</td>
              </tr>
              <tr>
                <td class="bitfield">10</td>
                <td class="symbol">H</td>
              </tr>
              <tr>
                <td class="bitfield">11</td>
                <td class="symbol">RESERVED</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;rotate&gt;</td><td><a id="sa_rotate"/>
        <p>Is the rotation, 
      encoded in
      <q>rot</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">rot</th>
                <th class="symbol">&lt;rotate&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">00</td>
                <td class="symbol">0</td>
              </tr>
              <tr>
                <td class="bitfield">01</td>
                <td class="symbol">90</td>
              </tr>
              <tr>
                <td class="bitfield">10</td>
                <td class="symbol">180</td>
              </tr>
              <tr>
                <td class="bitfield">11</td>
                <td class="symbol">270</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
bits(datasize) operand1 = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
bits(datasize) operand2 = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[m, datasize];
bits(datasize) operand3 = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[d, datasize];
bits(datasize) result;
<a href="shared_pseudocode.html#FPCRType" title="type FPCRType">FPCRType</a> fpcr = FPCR[];

for e = 0 to (elements DIV 2)-1
    bits(esize) element1;
    bits(esize) element2;
    bits(esize) element3;
    bits(esize) element4;
    case rot of
        when '00'
            element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index*2, esize];
            element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e*2, esize];
            element3 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index*2+1, esize];
            element4 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e*2, esize];
        when '01'
            element1 = <a href="shared_pseudocode.html#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index*2+1, esize]);
            element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e*2+1, esize];
            element3 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index*2, esize];
            element4 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e*2+1, esize];
        when '10'
            element1 = <a href="shared_pseudocode.html#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index*2, esize]);
            element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e*2, esize];
            element3 = <a href="shared_pseudocode.html#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index*2+1, esize]);
            element4 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e*2, esize];
        when '11'
            element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index*2+1, esize];
            element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e*2+1, esize];
            element3 = <a href="shared_pseudocode.html#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index*2, esize]);
            element4 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e*2+1, esize];

    <a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e*2, esize] = <a href="shared_pseudocode.html#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e*2, esize], element2, element1, fpcr);
    <a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e*2+1, esize] = <a href="shared_pseudocode.html#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e*2+1, esize], element4, element3, fpcr);

<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
    </p></body></html>
